1. Field of the Invention
This invention relates to semiconductor devices that provide semiconductor chips and components encapsulated in packages by resins. This invention also relates to methods of manufacturing semiconductor devices and packages.
2. Description of the Related Art
Recent progresses of electronic and information technologies provide a variety of electronic devices that use considerable numbers of semiconductor components installed therein in a highly concentrated manner. This brings a strong demand to downsize packages for encapsulating semiconductor components and chips in resins. Conventionally, so-called QFN packages (namely, quad flatpack non-leaded packages) are used to realize the downsizing of the packages. The QFN package eliminates outer leads, which were conventionally projected from side portions of the package, while providing external electrodes allowing electrical connections with the substrate on the lower surface thereof.
In order to ensure the airtightness, the packages are normally constituted of lead frames enclosed or sealed within resins. Japanese Patent No. 3012816 teaches a typical example of the QFN package in which both the upper and lower surfaces of the lead frame are sealed with a resin to increase the airtightness. Japanese Unexamined Patent Publication No. 2000-243891 teaches another example of the QFN package in which in order to improve the heat radiation or dissipation, the lower surface of the stage for supporting a semiconductor chip is exposed while the lead frame is enclosed or sealed within the resin.
As described above, the conventional packages are designed to enclose or seal semiconductor chips and lead frames within resins in various manners. However, the number of leads that can be provided for the package must be limited by the resin sealed area representing the prescribed portion of the package sealed within the resin. In order to secure the necessary number of leads, it is necessary to enlarge the resin sealed area, which may create difficulty in downsizing of the package.
In the general configuration of a semiconductor device that is sealed in a resin package, a semiconductor chip is electrically connected with terminals, which are partially exposed as electrodes. In this manner, the semiconductor chip and terminals are integrally assembled together in the resin package having ‘exposed’ electrodes. Conventionally, the terminals project from the side surfaces of the package of the semiconductor device. In response to the demand for increasing the number of terminals drawn out from the package and the demand for downsizing the package, recent semiconductor technology provides the so-called LGA type (wherein ‘LGA’ is an abbreviation for ‘Land Grid Array’), in which numerous terminals are aligned on the backside of the package, which is attached to and mounted on the board.
The outline of the manufacture of the semiconductor device of the LGA type will be described below.
FIG. 25 shows an example of a lead frame, or “frame,” that is conventionally used to produce a semiconductor device. FIG. 26 shows a selected part of the cross section of the semiconductor device that is produced using the frame of FIG. 25.
That is, the frame 205 provides a terminal support portion 251 roughly having a rectangular shape as an outer frame portion thereof. Herein, the prescribed number of inner terminals 202a are arranged along inner sides of the terminal support portion 251; and the prescribed number of outer terminals 202b are arranged along outer sides of the terminal support portion 251. That is, the inner terminals 202a project inwardly from the terminal support portion 251, and the outer terminals 202b project outwardly from the terminal support portion 251, wherein these terminals 202 are mutually interconnected and alternately project in opposite directions. Four stage supports 253 are extended inwardly from four corners of the terminal support portion 251, thus supporting a stage 252 that is arranged in the center area of the frame 205. It may be possible to omit the stage 252 and the stage supports 253 from the frame 205. FIG. 25 shows a typical example of the frame 205 that provides both of them.
A semiconductor chip 101 is fixedly mounted on the stage 252 of the frame 205 together forming a frame assembly. FIG. 26 shows that the semiconductor chip 101 is mounted on the stage 252 in a face-up mode. Herein, pads 101a of the semiconductor chip 101 are connected to backsides of the terminals 202a and 202b by fine lines 103 respectively. When the semiconductor chip 101 is mounted on the stage 252 in a face-down mode, the pads 101a of the semiconductor chip 101 are directly connected to the terminals 202 by solder bumps or solder balls.
Thus, it is possible to provide a frame assembly in which the semiconductor chip 101 is connected to the frame 205. The frame assembly is enclosed or sealed within a resin to form a package 104 under the condition where electrode surfaces 221 of the terminals 202 connected with the external circuit (not shown) are externally exposed. Then, the electrode surfaces 221 of the terminals 202 and the terminal support portion 251 of the frame 205 are both polished and removed by dicing. In this manner, the inner terminal 202a is separated from the outer terminal 202b. In the actual manufacture, there is provided a multiple interconnected frame assembly in which numerous units of the aforementioned frame assembly are interconnected together. Hence, outer peripheries of the outer terminals 202b are subjected to dicing, thus isolating each of the semiconductor devices. Reference symbol DG designates a dicing groove that is formed in the trace of the frame assembly from which the terminal support portion 251 has been removed by polishing.
When connecting the semiconductor device of the LGA type, which is produced as described above, with the external circuit, the lower surface (or mounting surface) of the semiconductor device is soaked into a solder bath, for example, wherein solder fillets are formed on the electrode surfaces 221 of the terminals 202 respectively. In this manner, the terminals 202 of the semiconductor device are connected with the terminals of the external circuit by solder fillets. However, the conventional semiconductor devices have various problems related to soldering. One such problem is caused by an ‘exposed’ terminal surface 223 of the terminal 202 that is exposed on a cut surface 141, which is formed by dicing the package 104, and is continuously formed in connection with the electrode surface 221. Because of this, when the semiconductor device is soaked into the solder bath, the solder adheres not only to the electrode surface 221 but also to the terminal surface 223, so that, as shown in FIG. 27A, these surfaces are continuously covered with a same solder fillet F. This prevents the constant amount of solder from being normally adhered to each terminal 202. In other words, this may cause deviations for joint strengths in the connection with the external circuit. In addition, the unstable consumption of solder may cause troubles for the production management of semiconductor devices. Another problem related to soldering is caused by the formation of a bridge that connects together the inner terminal 202a and the outer terminal 202b by a same fillet F as shown in FIG. 27B. In addition, a solder bridge may be formed between the terminal 202 and the terminal of the external circuit due to the excessive amount of solder adhering to the terminal 202 of the package 104. A further problem related to soldering is that when the semiconductor device is pulled up as shown in FIG. 27C after connected with the external circuit, the terminals 202 may be easily separated or isolated from the package 104.
Since the ‘metal’ terminals 202 are connected with the ‘resin’ package 104, their connecting ability is relatively small. This may cause a separation between the terminals 202 and the package 104 by a prescribed impact due to dicing. This problem may be solved by the technique of Japanese Unexamined Patent Publication No. 2000-286375, which will be described with reference to FIG. 27D. In that technique, the terminal support portion (or interconnecting portion) is removed from the backside of the package in advance, so that terminals (or connecting portions) 210 are isolated from each other; then, projecting portions 224 are provided on opposite side surfaces of the terminals 210, other sides of which are isolated from each other, in order to improve the adhesion between the terminals 210 and the package (or resin sealed member) 104 for the semiconductor device. However, this structure does not eliminate the continuation between the exposed terminal surface and electrode surface of the terminal 210. As a result, the aforementioned publication does not provide effective solutions for the aforementioned problems caused by deviations in the amounts of solder fillets F being adhered to the terminals and by formation of a bridge between the adjoining terminals. In addition, projecting portions cannot be formed on cut surfaces 141 by which the terminals 210 are isolated from each other. This would reduce the joint force effected between the terminals 210 and the package 104. Due to such insufficient joint force, when the semiconductor device is pulled up after connected with the external circuit, it could not avoid the separation between the terminals 210 and the package 104.